1. Field of the Invention
The present invention relates to an operation system of a central processing unit provided in a microcomputer or microprocessor.
2. Description of the Prior Art
FIG. 7 is a block diagram showing an arrangement of a microcomputer based on a conventional operation system. In FIG. 7, numeral 11 designates a central processing unit (which will be referred hereinafter to as a CPU) and 12 denotes a memory. The CPU 11 comprises a data latch circuit 5 for latching data for an operation from the memory 12, an arithmetic register 4 for storing data for operations and operation (calculation) results, a carry and borrow flag 2 for storing a carry indicative of the operation result to be stored in the arithmetic register 4 exceeding a predetermined number of bits and further for storing a borrow indicative of a digit (figure) borrow when the content of the data latch circuit 5 cannot be subtracted from the content of the arithmetic register 4, and an arithmetic and logic unit (which will be referred hereinafter to as an ALU) 3 for performing operations on the basis of the contents of the data latch circuit 5, the contents of the arithmetic register 4 and the contents of the carry and borrow flag 2 to store the operation results in the arithmetic register 4 and the carry and borrow flag 2. The CPU 11 performs the operations in accordance with programs written in the memory 12. The memory 12 comprises a ROM 12b for storing data and programs and a RAM 12a for temporarily storing data necessary for operations. Here, although the programs can be written in either the read-only ROM 12b or the readable and writable RAM 12a, it is general to write them in the ROM 12b. Accordingly, the following description will be made as the programs are written in the ROM 12b.
Secondly, the operation of the operation system will be described hereinbelow with reference to FIG. 7. The CPU 11 operates in accordance with a program written in the ROM 12b of the memory 12. In response to the CPU 11 reading operation codes on the program, the operation codes read are inputted to a control unit, not shown, of the CPU 11 and the control unit operates the CPU 11 in accordance with a procedure determined by the respective operation codes.
FIG. 8 is an illustration for describing an ADC instruction. The ADC instruction is an instruction for adding together the content of the arithmetic register 4, the content of the memory 12 and the content of the carry and borrow flag 2. Here, the content of the memory 12 means data stated as operands on a program within the memory 12, data written in the ROM 12b or data temporarily stored in the RAM 12a. The content "1" of the carry and borrow flag 2 before the operation indicates that the operation data takes a carry from a lower-order position, i.e., takes a figure up one place, and the content "0" of the carry and borrow flag 2 before the operation indicates that the operation data does not take the carry from the lower-order position. The calculation result is stored in the arithmetic register 4. In the case that the calculation result exceeds the number of bits of the arithmetic register 4, the content of the carry and borrow flag 2 becomes "1" at the time of the completion of the operation. On the other hand, in the case that the calculation result is below the number of bits of the arithmetic register 4, the content of the carry and borrow flag 2 becomes "0" at the time of the completion of the operation.
FIG. 9 is an illustration for describing an ADD instruction. The ADD instruction is an instruction for adding together the content of the arithmetic register 4 and the content of the memory 12. The calculation result is stored in the arithmetic register 4. In the case that the calculation result exceeds the number of bits of the arithmetic register 4, the content of the carry and borrow flag 2 becomes "1" at the time of the completion of the operation. In the case that the calculation result is below the number of bits of the arithmetic register 4, the content of the carry and borrow flag 2 becomes "0" at the time of the completion of the operation.
FIG. 10 is an illustration for describing an SBC instruction. The SBC instruction is an instruction for subtracting the content of the memory 12 and the content of the carry and borrow flag 2 from the content of the arithmetic register 4. The content "0" of the carry and borrow flag 2 before the operation indicates that the operation data takes a digit borrow from a lower-order position, and the content "1" of the carry and borrow flag 2 before the operation indicates that the operation data does not take the borrow from the lower-order position. The calculation result is stored in the arithmetic register 4. In the case that the content of the memory 12 and the content of the carry and borrow flag 2 cannot be subtracted from the content of the arithmetic register 4, that is, when a borrow occurs in the calculation result, the content of the carry and borrow flag 2 becomes "0" at the time of the completion of the operation. On the other hand, in the case that the borrow does not occur in the calculation result, the content of the carry and borrow flag 2 becomes "1" at the time of the completion of the operation.
FIG. 11 is an illustration for describing an SUB instruction. The SUB instruction is an instruction for subtracting the content of the memory 12 from the content of the arithmetic register 4. The calculation result is stored in the arithmetic register 4. In the case that the content of the memory 12 and the content of the carry and borrow flag 2 cannot be subtracted from the content of the arithmetic register, that is, when a borrow occurs in the calculation result, the content of the carry and borrow flag 2 becomes "0" at the time of the completion of the operation. When the borrow does not occur in the calculation result, the content of the carry and borrow flag 2 becomes "1" at the time of the completion of the operation.
For example, in the case that the ADC instruction is executed in an immediate addressing mode where an operand (operator) is stated in a program, when an operation code (instruction code) on the program is read and inputted to the CPU 11, the CPU 11 causes the operand to be latched as immediate value operation data (for example, DATA1) in the data latch circuit 5. The DATA 1 of the data latch circuit 5 passes through an internal bus 6a of the CPU 11 to be inputted to the ALU 3, the data (for example, DATA2) of the arithmetic register 4 passes through an internal bus 6b of the CPU 11 to be inputted to the ALU 3, and the data (for example, C1) of the carry and borrow flag 2 passes through a data line 7 to be inputted to the ALU3. The DATA1, DATA2 and C1 are added together in the ALU 3 and the calculation result (SUM) is inputted through the internal bus 6a of the CPU 11 to the arithmetic register 4. At this time, the output of the data latch circuit 5 is set to OFF. Further, the carry (for example, C2) of the calculation result is inputted through a data line 9 to the carry and borrow flag 2. The ADC instruction is completed with the aforementioned procedure.
Similarly, in the case of executing the ADD instruction in the immediate addressing mode, in response to an operation code on the program being read to the CPU 1 1, the CPU 11 causes the operand to be latched as the immediate value operation data DATA1 in the data latch circuit 5. The DATA1 of the data latch circuit 5 is inputted through the internal bus 6a of the CPU 11 to the ALU 3 and the data DATA2 of the arithmetic register 4 is inputted through the internal bus 6b of the CPU 11 to the ALU3. At this time, the carry input of the least significant bit of the ALU 3 is fixed to "0". The DATA 1 and the DATA 2 are added to each other in the ALU 3 and the calculation result SUM is inputted through the internal bus 6a of the CPU 11 to the arithmetic register 4. At this time, the output of the data latch circuit 5 is OFF. Further, the carry C2 of the calculation result is inputted through the data line 9 to the carry and borrow flag 2. The ADD instruction is completed with the aforementioned procedure.
Further, in the case of executing the SBC instruction in the immediate addressing mode, when an operation code on the program is read to the CPU 11, the CPU 1 1 causes the operand DATA1 to be latched as the immediate value in the data latch circuit 5. The DATA1 of the data latch circuit 5 is inputted through the internal bus 6a of the CPU 11 to the ALU 3 so as to be bit-inverted in the ALU 3 to become DATA1B. The data DATA2 of the arithmetic register 4 is inputted through the internal bus 6b of the CPU 11 to the ALU 3 and the data B1 of the carry and borrow flag 2 is inputted through the data line 7 to the ALU 3. The DATA1B, DATA2 and B1 are added together in the ALU 3, and the calculation result SUM is inputted through the internal bus 6a of the CPU 11. At this time, the output of the data latch circuit 5 is OFF. The SBC instruction is completed with the aforementioned procedure.
Still further, in the case of executing the SUB instruction in the immediate addressing mode, when an operation code on the program is read to the CPU 11, the CPU 11 causes the operand DATA1 to be latched as the immediate value in the data latch circuit 5. The DATA1 of the data latch circuit 5 is inputted through the internal bus 6a of the CPU 11 to the ALU 3 so as to be bit-inverted to be DATA1B in the ALU 3. The data DATA2 of the arithmetic register 4 is inputted through the internal bus 6b of the CPU 11 to the ALU 3. The data C1 of the carry and borrow flag 2 is inputted through the data line 7 to the ALU 3. At this time, the borrow input of the least significant bit of the ALU 3 is fixed to "1". The DATA1B and DATA2 are added together in the ALU 3, and the calculation result SUM is inputted through the internal bus 6a of the CPU 11 to the arithmetic register 4. At this time, the output of the data latch circuit 5 is OFF. Further, the borrow B2 of the calculation result is inputted through the data line 9 to the carry and borrow flag 2. The SUB instruction is completed with the aforementioned procedure.
As described above, the difference between the ADC instruction and the ADD instruction or the difference between the SBC instruction and the SUB instruction relates to whether the content of the carry and borrow flag to be inputted to the ALU 3 is effective or invalid, while the microcomputer based on the conventional operation system performs one operation determined by one operation code. Thus, for supporting the ADC instruction and the ADD instruction, different operation codes are required. It is similar in the cases of supporting the SBC instruction and the SUB instruction. Accordingly, there is a problem that, for supporting the effective operation of the carry input or borrow input and the invalid operation of the carry input or borrow input in a plurality of addressing modes, the number of the operation codes is required to double as compared with the case of supporting one of the operations.